1. Field of the Invention
The present invention relates to a semiconductor device of a multi-layered wiring structure, more specifically to a semiconductor device having a wiring designed by a design rule of a dummy pattern, the dummy pattern being formed with respect to a damaged region of the wiring by a via hole etching process, when the wiring is made of a material such as Cu or a Cu alloy, wherein the present invention is applied, for example, to a CMOSLSI (complementary MOS large-scale integration) circuit.
2. Description of the Related Art
In LSIs having a multi-layered wiring structure, Cu or its alloy has come to be used as a wiring material in place of conventionally-used Al, because the use of the Cu or its alloy helps decrease the resistance of wirings and vias and improves the reliability of them. In the case where the wirings and vias are made of Cu, however, the vias are likely to have open defects due to voids generated in the Cu wirings.
Where the wirings and vias made of Cu or a Cu alloy have a specific pattern, the voids are generated in the manufacturing step and the stress migration may be observed in a high-temperature test which is carried out at 225° C. and continued for 300 hours, for example. These will cause contact defects (disconnection or open defects), thereby degrading the performance of the manufactured semiconductor device.
The mechanism of the generation of such contact defects has not been made clear. A description will therefore be given of the phenomenon along with conceivable causes.
FIGS. 7A and 7B are plan views and schematically illustrate examples of patterns in which two wiring layers each having a wiring made of Cu or a Cu alloy and vias used for interlayer connection between the two wiring layers are arranged according to the prior art. The two wiring layers are part of a CMOSLSI of multi-layered wiring structure. In FIGS. 7A and 7B, reference numeral 71 denotes a lower wiring (Cu wiring), reference numeral 72 denotes an upper wiring (a Cu wiring), and reference numeral 73 denotes a via for interlayer connection between the cu wirings 71 and 72.
FIG. 7A illustrates a structure wherein the wide lower wiring 71 (whose width W is greater than a predetermined value) is connected to the upper wiring 72 through the single via 73. If a product having this structure undergoes stress migration in a high-temperature test, the via 73 has a contact defect (an open or disconnection defect).
FIG. 7B illustrates a structure wherein the wide lower wiring 71 (whose width W is greater than a predetermined value) is joined to a narrow lower wiring 71a (whose width Wn is not more than a predetermined value) in the same lower wiring layer, and wherein the upper wiring layer 72 is connected to the narrow lower wiring layer 71a through the single via 73. If a product having this structure undergoes stress migration in a high-temperature test, the via 73 has the similar contact defect.
FIGS. 8A and 8B are sectional views schematically illustrating how the Cu crystals of a narrow lower Cu wiring that is not joined to a wide lower Cu wiring (unlike that 71a shown in FIG. 7B) will be changed before and after heat treatment. In the case shown in FIGS. 8A and 8B, no void is generated even after the heat treatment
FIGS. 9A and 9B are sectional views schematically illustrating how the Cu crystals of the wide lower Cu wiring 71 shown in FIGS. 7A and 7B will be changed before and after heat treatment. In the case shown in FIGS. 9A and 9B, a void 90 is generated in the wiring 71 after the heat treatment.
FIG. 10 shows an example of a contact defect (disconnection or open defect) of a via 73 connected to the lower wiring (Cu wiring) 71 (or 71a) shown in FIGS. 7A and 7B. In FIG. 10, reference numerals 74 and 75 denote barrier metal films.
In the case where a via hole (for the via 73) is formed in an interlayer insulation film (not shown) on the lower wiring 71 (71a) by reactive ion etching (RIE) and is then subjected to heat treatment, the exposed surface region of the wiring 71 (71a) at the bottom of the via hole is damaged or stressed due to the etching or heat treatment after the formation of the via hole. When Cu crystal grains are grown in the subsequent annealing process, contact defects (open defects) are caused in the wide lower wiring 71 shown in FIG. 7A and in the narrow lower wiring 71a shown in FIG. 7B joined to the wide lower wiring 71, because the bottoms (damaged regions 100) of the via holes in such wiring undergo damage or stress and voids 90 are concentratedly moved.
The conventional semiconductor device described above has a multi-layered wiring structure wherein the wirings and vias formed in the wiring layers are made of Cu or Cu alloy. In the case where a via formed in an upper wiring layer is connected to a wide wiring formed in the lower wiring layer, the connection between the via and lower wide wiring may suffer a contact defect (degraded reliability) arising from the heat treatment of the manufacturing process.
In an effort to solve the problems described above, the Assignee of the present application has proposed a semiconductor device in Japanese Patent Application No. 2002-212908. The semiconductor device in this patent application comprises multi-layered wirings made of Cu or a Cu alloy. When a wide lower wiring formed in a lower wiring layer is connected to an upper wiring through a via formed in the upper wiring layer, predetermined restrictions are defined on the design rules of the wirings and the vias in such a way as to increase the reliability of the multi-layered wirings.
In the proposed semiconductor device described above, the multi-layered wiring structure formed on the semiconductor substrate comprises a plurality of wiring layers each including a wiring made of Cu or an Cu alloy, and a via formed through a wiring layer. In order to prevent a via (which is used for connecting a lower wiring layer to an upper wiring layer) from having a contact defect, the following design rules are adopted:
(1) the number of contacts or vias connecting to a lower wiring from an upper wiring is determined in accordance with the width of the lower wiring or the volume of this lower wiring.
(2) In the case where a wide lower wiring is joined to a narrow lower wiring in the same wiring layer, the voids that are generated on wide lower wiring are likely moved to narrow lower wiring joined to wide lower wiring. With this in mind, the number of contacts or vias leading to the lower wiring is determined in accordance with the wiring width or volume of the narrow lower wiring.
According to one of these design rules, two or more interlayer-connection vias are formed if an open defect is likely at a single via. The region where the two or more interlayer-connection vias are formed is a void effective diffusion region. In this region, voids in the Cu wiring are generated concentratedly and a contact defect is likely to occur in the via bottom damaged or stressed by the etching performed when a via hole is formed and by the heat treatment performed after the via hole is formed.
By forming two or more vias as above-mentioned, voids generated in the lower wiring at the time of heat treatment, are distributed to the bottom regions of the vias. The via where the more voids are concentrated serves as a redundancy via, so that the contact characteristics of the other via or vias do not deteriorate, and the reliability of the semiconductor device is not adversely affected.
Even if two or more interlayer-connection vias are formed, they do not function as such. That is, it is necessary to presume that an open defect is caused in one of the vias. In addition to this design restriction, the number of vias to be formed has to be determined, depending upon whether or not a wide lower wiring is continuous with a narrow lower wiring at the same wiring layer.